Many tests of vasp.6.4.2 compiled on AMD epyc 9554 failed.
Posted: Wed Apr 17, 2024 8:54 am
Hi here,
My machine and OS information are as follows:
I compiled vasp.6.4.2 using intel oneAPI 2023.2.0 with the following makefile.include which is adapted from makefile.include.intel:
The compilation succeeded, but the following tests failed while running make test:
I've attached the related files mentioned above.
Regards,
Zhao
My machine and OS information are as follows:
Code: Select all
$ inxi -MCS
System:
Host: MZ73-LM1-000 Kernel: 6.5.0-18-generic x86_64 bits: 64
Desktop: GNOME 42.9 Distro: Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Machine:
Type: Server System: Giga product: MZ73-LM1-000 v: 0100
serial: <superuser required>
Mobo: Giga model: MZ73-LM1-000 v: 01000100 serial: <superuser required>
UEFI: GIGABYTE v: F12 date: 09/07/2023
CPU:
Info: 2x 64-core model: AMD EPYC 9554 bits: 64 type: MT MCP SMP cache:
L2: 2x 64 MiB (128 MiB)
Code: Select all
# Default precompiler options
CPP_OPTIONS = -DHOST=\"LinuxIFC\" \
-DMPI -DMPI_BLOCK=8000 -Duse_collective \
-DscaLAPACK \
-DCACHE_SIZE=4000 \
-Davoidalloc \
-Dvasp6 \
-Duse_bse_te \
-Dtbdyn \
-Dfock_dblbuf
CPP = fpp -f_com=no -free -w0 $*$(FUFFIX) $*$(SUFFIX) $(CPP_OPTIONS)
FC = mpiifort
FCL = mpiifort
FREE = -free -names lowercase
FFLAGS = -assume byterecl -w
OFLAG = -O2
OFLAG_IN = $(OFLAG)
DEBUG = -O0
OBJECTS = fftmpiw.o fftmpi_map.o fftw3d.o fft3dlib.o
OBJECTS_O1 += fftw3d.o fftmpi.o fftmpiw.o
OBJECTS_O2 += fft3dlib.o
# For what used to be vasp.5.lib
CPP_LIB = $(CPP)
FC_LIB = $(FC)
CC_LIB = icc
CFLAGS_LIB = -O
FFLAGS_LIB = -O1
FREE_LIB = $(FREE)
OBJECTS_LIB = linpack_double.o
# For the parser library
CXX_PARS = icpc
LLIBS = -lstdc++
##
## Customize as of this point! Of course you may change the preceding
## part of this file as well if you like, but it should rarely be
## necessary ...
##
# When compiling on the target machine itself, change this to the
# relevant target when cross-compiling for another architecture
#VASP_TARGET_CPU ?= -xHOST
# For 4th generation EPYC:
#https://www.vasp.at/forum/viewtopic.php?p=25947#p25947
#https://www.amd.com/content/dam/amd/en/documents/developer/compiler-options-quick-ref-guide-amd-epyc-9xx4-series-processors.pdf
VASP_TARGET_CPU ?= -axCORE-AVX512
FFLAGS += $(VASP_TARGET_CPU)
# Intel MKL (FFTW, BLAS, LAPACK, and scaLAPACK)
# (Note: for Intel Parallel Studio's MKL use -mkl instead of -qmkl)
FCL += -qmkl=sequential
MKLROOT ?= /path/to/your/mkl/installation
LLIBS += -L$(MKLROOT)/lib/intel64 -lmkl_scalapack_lp64 -lmkl_blacs_intelmpi_lp64
INCS =-I$(MKLROOT)/include/fftw
# HDF5-support (optional but strongly recommended)
#CPP_OPTIONS+= -DVASP_HDF5
#HDF5_ROOT ?= /path/to/your/hdf5/installation
#LLIBS += -L$(HDF5_ROOT)/lib -lhdf5_fortran
#INCS += -I$(HDF5_ROOT)/include
# For the VASP-2-Wannier90 interface (optional)
#CPP_OPTIONS += -DVASP2WANNIER90
#WANNIER90_ROOT ?= /path/to/your/wannier90/installation
#LLIBS += -L$(WANNIER90_ROOT)/lib -lwannier
#Re: Clarification Request on Configuring DFT-D4 Support in VASP.
#https://www.vasp.at/forum/viewtopic.php?p=25763#p25763
#CPP_OPTIONS += -DDFTD4
#DFTD4_ROOT ?= /path/to/your/dft4/installation
## version 3.6.0 built and installed with meson
##LLIBS += $(shell pkg-config --with-path=$(DFTD4_ROOT)/lib64/pkgconfig --libs dftd4)
##INCS += $(shell pkg-config --with-path=$(DFTD4_ROOT)/lib64/pkgconfig --cflags dftd4)
## version 3.6.0 and loaded dftd4 module, i.e. PKG_CONFIG_PATH environment variable set correctly
#LLIBS += $(shell pkg-config --libs dftd4)
#INCS += $(shell pkg-config --cflags dftd4)
Code: Select all
$ VASP_TESTSUITE_TESTS="bulk_InP_SOC_G0W0_sym bulk_InP_SOC_G0W0_sym_RPR bulk_SiO2_LOPTICS bulk_SiO2_LOPTICS_RPR bulk_SiO2_LPEAD bulk_SiO2_LPEAD_RPR SiC8_GW0R Tl_x Tl_x_RPR Tl_y Tl_y_RPR Tl_z Tl_z_RPR" make test
[...]
==================================================================
SUMMARY:
==================================================================
The following tests failed, please check the output file manually:
bulk_InP_SOC_G0W0_sym bulk_InP_SOC_G0W0_sym_RPR bulk_SiO2_LOPTICS bulk_SiO2_LOPTICS_RPR bulk_SiO2_LPEAD bulk_SiO2_LPEAD_RPR SiC8_GW0R Tl_x Tl_x_RPR Tl_y Tl_y_RPR Tl_z Tl_z_RPR
Regards,
Zhao